{"id":5312,"date":"2025-03-05T10:14:04","date_gmt":"2025-03-05T01:14:04","guid":{"rendered":"https:\/\/www.phys.s.u-tokyo.ac.jp\/en\/?p=5312"},"modified":"2025-03-05T10:14:04","modified_gmt":"2025-03-05T01:14:04","slug":"proposal-for-a-new-quantum-computer-architecture-that-separates-the-memory-and-processor","status":"publish","type":"post","link":"https:\/\/www.phys.s.u-tokyo.ac.jp\/en\/news\/5312\/","title":{"rendered":"Proposal for a new quantum computer architecture that separates the memory and processor"},"content":{"rendered":"
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Takumi Kobori, a graduate student (an intern at Nippon Telegraph and Telephone Corporation at the time) and\u00a0Professor Synge Todo<\/a>\u00a0of the Graduate School of Science at The University of Tokyo, Researchers Yasunari Suzuki and Yuuki Tokunaga of Nippon Telegraph and Telephone Corporation, Research Fellow Yosuke Ueno of the RIKEN Quantum Computer Science Institute, and Associate Professor Teruo Tanimoto of the Graduate School of Systems Information Science, Kyushu University, have proposed a new architecture for error-tolerant quantum computation that applies the basic design of conventional computers to quantum computers. Associate Professor Teruo Tanimoto and his research group have proposed a new architecture for error-tolerant quantum computation that applies the basic design of conventional computers, the load-store computing concept, to quantum computers. This technology is expected to accelerate the early realization of useful quantum computation by enabling high portability of programs (ease of migration to other environments) and utilization of highly efficient quantum hardware. The results were presented at The 31st IEEE International Symposium on High-Performance Computer Architecture (HPCA2025), which is being held from March 1, 2025.<\/p>\n\n\n\n

See below for more information.<\/p>\n\n\n\n